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Keywords: DFT (Design For Test) Engineer, Location: San Jose, CA

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DFT (Design For Test) Engineer

DFT (Design for Test) Engineer About Etched We are seeking a highly skilled and motivated Design For Testability... and Implementation Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage...

Company: Etched
Location: San Jose, CA
Posted Date: 10 Apr 2025
Salary: $2000 per month

Senior Principal Design Engineer - DFT

Principal Design Engineer will define the DFT Architecture for the next generation SoCs. This person will also be responsible... of 5 years of experience At least 8 years of relevant hands-on experience in Design for Test (DFT). Clear understanding...

Posted Date: 16 Apr 2025

Sr Product Test Development Engineer

. Apply sophisticated data analytics to optimize test efficiency and drive yield improvements. Collaborate with Design, SoC, DFT... and highlight issues You're Impact You will be a Sr Product Test Development Engineer in Silicon Operations focusing on the...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 01 May 2025

Hardware Test Engineer (Nextest, San Jose, CA)

to ensure products are built free of manufacturing defects. Understanding of DFT (Design for Test) and DFM (Design... within an open collaborative peer environment. As a Hardware Test Engineer you will be responsible for defining and implementing...

Company: Teradyne
Location: San Jose, CA
Posted Date: 25 Apr 2025
Salary: $82900 - 132600 per year

Senior Test Engineer - 93k Exp Required

an exceptional Senior Test Engineer to join our Operations team in San Jose Office. In this role, you will be working... with design to ensure good Test coverage. Effective communications skills with internal cross functional teams, customers...

Company: Rambus
Location: San Jose, CA
Posted Date: 13 Apr 2025
Salary: $120200 - 180400 per year

Senior Test Engineer

-signal power management semiconductor products. Work with IC design team to understand design specifications and DFT... proposals. Create test programs in C language, debug and validate silicon on ATE Design test interface hardware...

Location: San Jose, CA
Posted Date: 20 Mar 2025
Salary: $109023 - 150000 per year

Senior RTL Design Engineer (remote)

Senior RTL Design Engineer Remote / work from home US Citizen or US Permanent Resident Full-time/employee + Benefits... specifications based on the SoC requirements Design, implement and integrate complex SoC blocks Develop block-level test cases...

Location: San Jose, CA
Posted Date: 04 May 2025

ASIC Design Engineer - Design & Timing Constraints

a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing... is filled or if a sufficient number of applications are received. Meet the Team Join our dynamic front-end design team...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 24 Apr 2025

Senior ASIC Design Verification Engineer

With You will work with outstanding talent and vast ASIC development expertise in design, DV, DFT, physical design, and post-silicon... arrival through system validation to first customer shipments. What You'll Do You will participate in the ASIC design...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 05 Mar 2025

Photonics IC Design Engineer

: You are a subject matter expert and strong technical contributor with PIC theory, design, layout, simulation, packaging, debug, test... test requirements. Assess risks and mitigations with quantified Process and Design FMEAs. Evaluate field returns...

Posted Date: 26 Feb 2025

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock...: Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 01 Apr 2025

Senior E/E & Semiconductor Engineer - Post Silicon Validation Engineer

engineering. Strong fundamentals in IC design, Design for Test, and manufacturing concepts. Low level C, C++, RISV-V assembler...! Knowledge of test cell integration and production test program release! Proven understanding of the latest DFT and test...

Company: Capgemini
Location: San Jose, CA
Posted Date: 13 Apr 2025

NPI Product Engineering

. Basic knowledge of DFT (Design For Test). Skills in programming is a plus (Phython, PERL, C++) Additional... including design, test, and manufacturing to ensure customer delivery. Ensures optimal yield while delivering to test time...

Company: Broadcom
Location: San Jose, CA
Posted Date: 18 Apr 2025
Salary: $94000 - 150000 per year

ASIC Engineering Technical Leader - SDC

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock...: Oversee fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing modes...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 02 Apr 2025