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Keywords: Design-for-Test (DFT) Engineer, Location: Santa Clara, CA

Page: 2

Senior ASIC Synthesis Engineer

across multiple design blocks Work with DFT and Verification teams to ensure functional and timing correctness What we need... to stand out from the crowd: Knowledge of DFT/Test logic including JTAG, scan, high speed I/O loopback, and memory...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 03 Jul 2025

Principal Static Timing Analysis (STA) Engineer

(PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), RTL Design and other cross... a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Jun 2025
Salary: $124420 - 186400 per year

Mechanical Design Engineer (Tooling Design Focus)

Introduction) into global manufacturing environments. Engineer, design, and validate custom tooling, test fixtures, and jigs... of quality and performance in everything we do. Job Description Who You'll Work With As a Mechanical Design Engineer...

Company: Arista Networks
Location: Santa Clara, CA
Posted Date: 25 Jun 2025
Salary: $100000 - 175000 per year

System Software Engineer - DFX Software

of Design for Test (DFT) including fault models, ATPG, and fault simulation Familiarity with creating scalable, containerized...We are now looking for a Systems Software Engineer. Do you like to think creatively and enjoy solving challenges...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Jun 2025

Senior DFX Software Engineer - Machine Learning

We are now looking for a Senior Software Engineer - Design-For-Test. Do you like to think creatively and enjoy solving... software in modern C++ and various scripting languages to enable design and development of software enabling efficient test...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Jun 2025

RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... simulation tools Proficient in creating unit level test benches for pre-qualification of design. Knowledge of RTL quality...

Posted Date: 12 Jun 2025

Senior ASIC Timing Engineer

on all aspects of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation... advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ensure design quality. • Build and Test Infrastructure: Develop...

Company: Apple
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

ASIC Design Engineer

design flow including front end design and verification, DFT, timing analysis, ECO, ATE test development, post-si bringup...NVIDIA is looking for an ASIC Design Engineer to join our Global Circuits Team! In this position, you'll make a real...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 May 2025

Senior ASIC Design Engineer - DFX

to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT...We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 May 2025

Test Engineer

next-generation high-speed packaging and test strategies in collaboration with design, DFT, and product engineering teams... engineer in the Operations business group, you will test features on the silicon semiconductor chips Marvell produces...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 20 May 2025
Salary: $115790 - 173500 per year

Senior Optical packaging design engineer

Cycle (PLC) process by defining Design For Transportability (DFT) requirements and influencing product design. Identify... new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers...

Location: Santa Clara, CA
Posted Date: 15 May 2025
Salary: $138000 - 183500 per year

Custom Circuits Design Engineer

for the test chips and product chips. • Perform design analysis, modeling/simulation, spice simulation, statistical analysis... will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never...

Company: Apple
Location: Santa Clara, CA
Posted Date: 01 Aug 2025

Standard Cell Design Methodology & Flow Engineer

to Design For Test, scan concept and write DFT friendly RTL Understands all aspects of implementation specification, design...Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jul 2025

Senior Circuit Design Engineer

circuits, e.g. power gating, decaps, multi-vt is required. Understanding of Design-for-test (DFT) and logic design...! What you'll be doing: Participate in cutting edge Processor design in deep submicron technologies. Work as part of a global...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 13 Jul 2025

ASIC Design Engineer

Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test... cases for the module level and chip level. Participate in FPGA emulation and post-silicon validation. Write design...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 22 Jun 2025
Salary: $120000 - 145000 per year