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Keywords: RTL Design Engineer, Location: San Jose, CA

Page: 1

DSP or Serdes RTL Sr Principal Digital Design Engineer

. This includes but is not limited to: Digital microarchitecture definition and documentation RTL logic design, debug and functional... and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate...

Posted Date: 19 Jul 2025

Senior RTL Design Engineer

your career. THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive..., you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package...

Posted Date: 08 Oct 2025

GPU RTL Design Engineer

of people around the world. Come build with us! Role and Responsibilities As a GPU RTL Design Engineer, you will work... with driving the RTL design of various sub-blocks for a GPU targeted to mobile market. Significant architectural, as well as RTL...

Company: Samsung
Location: San Jose, CA
Posted Date: 13 Aug 2025

High Speed RTL Design Engineer

Engineering or Computer Engineering with 10+ years of experience in high speed ADC based SerDes RTL design. Proficient...Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include: MS or PhD in Electrical...

Company: Broadcom
Location: San Jose, CA
Posted Date: 09 Oct 2025

ASIC/RTL Design Engineer - Senior (US)

of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: San Jose, CA
Posted Date: 26 Sep 2025

ASIC/RTL Design Engineer - Senior (US)

of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: San Jose, CA
Posted Date: 25 Sep 2025

RTL Design Engineer

_ THE ROLE: We are seeking a Logic Design Expert with strengths in RTL and Timing and preferably with a background in DFx.... You have had significant success driving Design Methodologies, RTL, Timing and Architecture to tape out and production...

Posted Date: 24 Sep 2025

ASIC RTL Design Technical Lead

RESPONSIBILITIES: As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: Write microarchitecture... and/or design specifications Design, implement, and debug complex logic designs Integrate complex IPs into the SOC Work...

Posted Date: 08 Oct 2025

RTL Synthesis Engineer

Broadcom is looking for a senior level RTL synthesis engineer. In this highly visible role, you will be contributing... or Computer Engineering with 6+ years of experience in Physical design. Expert in Logic/Physical Synthesis using advanced...

Company: Broadcom
Location: San Jose, CA
Posted Date: 09 Oct 2025
Salary: $120000 - 192000 per year

SOC RTL Integration Engineer

_ THE ROLE: Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying... and quality THE PERSON: We are currently seeking professionals with experience in SOC RTL or Front-End integration, possessing...

Posted Date: 30 Sep 2025

Senior DFx/RTL Engineer

-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT... testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 22 Jul 2025

Senior Applications Engineer – DDR Design IP

Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog...

Posted Date: 10 Oct 2025
Salary: $84000 - 156000 per year

Lead Applications Engineer – DDR Design IP

. As a Lead Technical Presales Engineer, you will use your knowledge of different memory interface standards to architect memory... and designers · Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit...

Posted Date: 05 Oct 2025
Salary: $102900 - 191100 per year

Senior Applications Engineer – DDR Design IP

Applications Engineer – DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading... Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog...

Posted Date: 05 Oct 2025
Salary: $84000 - 156000 per year

ASIC Design Engineer Staff

ASIC Design Engineer Staff This role has been designed as 'Hybrid' with an expectation that you will work... phases. Work with Physical design team for optimal floorplan and timing closure. Identify and fix timing in RTL to meet the...

Posted Date: 09 Oct 2025

Sr. Physical Design Engineer

fast. Location of Job: Santa Clara County Job Title: Sr. Physical Design Engineer Duties: Requiring limited... for influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach Work closely with vendor...

Company: Groq
Location: San Jose, CA
Posted Date: 08 Oct 2025

ASIC Design Engineer Staff

ASIC Design Engineer Staff This role has been designed as ‘Hybrid’ with an expectation that you will work... phases. Work with Physical design team for optimal floorplan and timing closure. Identify and fix timing in RTL to meet the...

Posted Date: 08 Oct 2025

IP Design Engineer - AMDJP00004415

Job Title: IP Design Engineer Position is 100% remote Interview process is with MS Teams Client: Semiconductor...: 7 to 12 years of experience in digital design RTL coding experience using Verilog and/or System Verilog...

Company: Seneca Resources
Location: San Jose, CA
Posted Date: 03 Oct 2025

GPU Formal Design Verification Engineer

solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation..., FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include...

Company: Prodapt
Location: San Jose, CA
Posted Date: 24 Sep 2025

GPU Formal Design Verification Engineer

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 23 Sep 2025