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Keywords: RTL Design Engineer, Location: Santa Clara, CA

Page: 2

ASIC Design Efficiency Engineer

We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers...) improvements. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Jun 2025

Senior Staff Engineer, Physical Design

-outs and help drive Marvell’s continued leadership in the semiconductor industry. Your collaboration with the RTL design.... Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience with digital logic...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Jun 2025
Salary: $124420 - 186400 per year

GPU Logic Design Engineer

efficient low latency designs with scalabilities and flexibilities Power and Area efficient RTL logic design and DV support... and system verilog, synthesizable RTL Knowledgeable in modern design techniques and energy-efficient/low power logic design...

Company: Intel
Location: Santa Clara, CA
Posted Date: 08 Jun 2025

ASIC Design Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL/micro-architecture...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Jun 2025

GPU Design Engineer - Memory Hierarchy

! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade... help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Jun 2025

SoC Design Engineer

We seek a skilled front-end SoC design engineer. A customer driven professional with a track record of effective..., Performance and Area) requirements. Your tasks may include: architecture - micro-architecture; logic design; RTL integration...

Posted Date: 01 Jun 2025

Senior Staff Physical Design Engineer - Static Timing Analysis

a Senior Staff Physical Design Engineer – Static Timing Analysis (STA) to join our growing team. In this role...-functional teams including RTL design, synthesis, and physical implementation to ensure on-time and high-quality tape-outs...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 31 May 2025
Salary: $124420 - 186400 per year

ASIC Design Engineer

NVIDIA is looking for an ASIC Design Engineer to join our Global Circuits Team! In this position, you'll make a real... of our Global Circuits Team, you will be responsible for the micro-architecture and digital design implementation of various...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 May 2025

Senior ASIC Design Engineer - DFX

We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades... in SOC architecture and design experience. Experience in micro-architecture and RTL development (Verilog). Verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 May 2025

Silicon Design Engineer

cause; work with RTL and firmware engineers to resolve design defects and correct any test issues PREFERRED EXPERIENCE... in RTL testing (UVM concepts, dynamic test generation, directed test development etc.) Proficient in debugging firmware...

Posted Date: 25 Jul 2025

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... and high performance. Knowledge of Cache design/architecture, memory hierarchy is a huge plus. Working knowledge of RTL...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Jul 2025

SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis..., and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowledge...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 17 Jul 2025
Salary: $110600 - 140000 per year

GPU Physical Design Engineer

, being responsible for implementing complete chip design from RTL to tapeout. Description - Work closely with the FE team... to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback. Use...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Jul 2025

Standard Cell Design Methodology & Flow Engineer

to Design For Test, scan concept and write DFT friendly RTL Understands all aspects of implementation specification, design...Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jul 2025

Senior Staff Physical Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Physical Design team... is located in our Santa Clara, CA office, and has a long history of successful design tapeouts in advanced process nodes...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 02 Jul 2025
Salary: $124420 - 186400 per year

SoC Design Engineer

, micro architecture design, RTL design and hardware/software co-simulation. Perform software algorithm validation and cost...Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 26 Jun 2025
Salary: $151091 - 155000 per year

SoC Design Engineer

, micro architecture design, RTL design and hardware/software co-simulation; Work with algorithm and application engineers...Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 25 Jun 2025
Salary: $151091 - 155000 per year

ASIC Design Engineer

Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test... cases for the module level and chip level. Participate in FPGA emulation and post-silicon validation. Write design...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 22 Jun 2025
Salary: $120000 - 145000 per year

Principal Engineer, Physical Design

of developing and implementing intricate timing and logic ECOs. Collaboration is key, and you will work closely with the RTL design... logic course and projects that involved circuit design, testing, and timing analysis. Strong understanding of standard RTL...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 18 Jun 2025
Salary: $146850 - 220000 per year

GPU Design Engineer - Memory Hierarchy

help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll.... Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 12 Jun 2025