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Keywords: RTL Synthesis Engineer, Location: San Jose, CA

Page: 1

RTL Synthesis Engineer

Broadcom is looking for a senior level RTL synthesis engineer. In this highly visible role, you will be contributing... or Computer Engineering with 6+ years of experience in Physical design. Expert in Logic/Physical Synthesis using advanced...

Company: Broadcom
Location: San Jose, CA
Posted Date: 06 Aug 2025
Salary: $120000 - 192000 per year

Senior RTL Design Engineer

Design Engineer and experience in RTL coding, synthesis, and/or SoC integration Familiarity with digital design..., which employs over 32,000 people across 80+ locations globally. Prodapt is looking for a Senior RTL Design Engineer who has recent...

Company: Prodapt
Location: San Jose, CA
Posted Date: 21 Aug 2025

Senior RTL Design Engineer

, or equivalent with Minimum 10+ years of experience as a Digital Design Engineer and experience in RTL coding, synthesis, and/or SoC... is looking for a Senior RTL Design Engineer who has recent experience working on complex SoCs using RTL Coding from Scratch, Microarchitecture...

Company: Prodapt
Location: San Jose, CA
Posted Date: 20 Aug 2025

Senior RTL Design Engineer

_ THE ROLE: We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve..., you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package...

Posted Date: 27 Jun 2025

DSP or Serdes RTL Sr Principal Digital Design Engineer

. This includes but is not limited to: Digital microarchitecture definition and documentation RTL logic design, debug and functional... synthesis timing constraints, static timing analysis and constraint development Understanding of fundamental physical design...

Posted Date: 19 Jul 2025

High Speed RTL Design Engineer

Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include: MS or PhD in Electrical... Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design. Proficient...

Company: Broadcom
Location: San Jose, CA
Posted Date: 12 Jul 2025
Salary: $120000 - 192000 per year

Digital Design Engineer

of What's Possible™. Learn more at and on and . Digital Design Engineer About the Role As a Digital Design Engineer, you will design... and project execution skills. Key Responsibilities Perform independent RTL design and verification of digital modules Execute...

Company: Analog Devices
Location: San Jose, CA
Posted Date: 28 Aug 2025
Salary: $99360 - 136620 per year

Senior Staff Emulation Engineer - ZEBU

services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design..., UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up...

Company: Prodapt
Location: San Jose, CA
Posted Date: 20 Aug 2025

Senior Staff Emulation Engineer - ZEBU

. The engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving synthesis and P&R... solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation...

Company: Prodapt
Location: San Jose, CA
Posted Date: 20 Aug 2025

STA/SDC Engineer

Job Title: STA/SDC Engineer Duration: 12+ Months Location: San Jose, CA Technical: Being a member of design team... modes. Option to also do block level RTL design or block or top-level IP integration. Helping develop efficient...

Posted Date: 07 Aug 2025

IC Design Engineer

Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture... definition Perform RTL design using Verilog HDL, with an emphasis on performance and area Implement multi-power and low-power...

Company: Broadcom
Location: San Jose, CA
Posted Date: 04 Jul 2025
Salary: $120000 - 192000 per year

Senior ASIC Design Engineer (eInfochips Inc)

Position: Senior ASIC Design Engineer (eInfochips Inc) Job Description: What candidate will Be Doing: Map multi... methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design...

Location: San Jose, CA
Posted Date: 11 Jun 2025

Principal Product Engineer

. You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to GDSII.... This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG...

Posted Date: 11 Jun 2025

SDC Engineer (eInfochips Inc)

Position: SDC Engineer (eInfochips Inc) Job Description: Position: SDC Engineer (eInfochips Inc) Location: San... with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do block level RTL design...

Location: San Jose, CA
Posted Date: 07 Jun 2025

STA Engineer

Job Requirements You will be responsible for macro level RTL to gds implementation and signoff. Work with Front-End..., including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. Optimize designs...

Company: Quest Global
Location: San Jose, CA
Posted Date: 16 Aug 2025

ASIC Design Engineer

to close fullchip timing in multiple timing modes. Option to also do block level RTL design or block or top-level IP... as possible in design cycle. Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 08 Aug 2025
Salary: $60 - 70.97 per hour

IC Physical Design Flow, Principal Solutions Engineer - AE

Compiler) Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) Experience with EDA tools in the IC... technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place...

Posted Date: 19 Jul 2025
Salary: $123200 - 228800 per year

R&D Engineer IC Design

you are responsible for 1. Design, RTL coding, and IP integration of key components like Digital Delay Lines, Encoders/Decoders, PRBS... GEN / Check, Clock Spines, PHYs 2. Interface with other Layout, RTL, SI etc engineers to implement & integrate the...

Company: Broadcom
Location: San Jose, CA
Posted Date: 03 Jul 2025
Salary: $120000 - 192000 per year

Contract Hardware Engineer Sr

to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top.... Proficiency in synthesis, place, and route flows for FPGAs. An in-depth knowledge of digital design concepts, including Clock...

Company: LanceSoft
Location: San Jose, CA
Posted Date: 15 Jun 2025

FPGA/ASIC Engineer

methodology. Option to engage in block-level RTL design or block or top-level IP integration. Collaborate with Software, Design... expertise in partitioning multi-million gate designs across multiple FPGAs. Proficiency in synthesis, place, and route flows...

Company: Nesco Resource
Location: San Jose, CA
Posted Date: 15 Jun 2025