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Keywords: Senior STA Engineer, Location: Bangalore, Karnataka

Page: 1

Senior Staff STA Engineer

industry standard tools. What You Can Expect As a STA engineer you will be part of our signoff team responsible for signing... ASICs for all the OEM’s. We are looking for a strong technical individual contributor having experience in STA using...

Company: Marvell
Posted Date: 16 Nov 2025

Senior STA Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.... Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis...

Company: Qualcomm
Posted Date: 16 Nov 2025

STA CAD Engineer, Senior

. Job Title: STA CAD Engineer Location: Bangalore Department: GCAD Job Type: Full-Time Experience Level: 2-4 years... Job Summary: We are seeking a highly motivated STA CAD Engineer to join our CAD/EDA team. The ideal candidate...

Company: Qualcomm
Posted Date: 08 Nov 2025

Senior STA Engineer

Summary: The Digital Physical Design Engineer is responsible for a physical implementation of IP, Subsystem or IC.... Should have worked on Genus flows. Should be good in STA flow setup and STA flows. Should have worked in Tempus flows...

Posted Date: 06 Nov 2025

DFT Sr Engineer - MBSIT, ATPG - STA constraints timing

your career. SENIOR SILICON DESIGN ENGINEER / MTS The Role: As a key member of the S3 SoC DFT Team, the successful candidate... and DFT STA constraints. STA constraint development of DFT modes (ScanShift, Atspeed, MBIST) Set up DFT timing constraints...

Posted Date: 19 Oct 2025

STA Synthesis Lead

your career. SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role will involve driving the physical design flow..., and area (PPA) targets on SerDes PHY IPs. THE PERSON: As a senior member of the SerDes IP Physical Design team...

Posted Date: 01 Nov 2025

Senior DFT Engineer, SSG

of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part... leadership in taking chips from design to volume production. As a Senior DFT Engineer, you will be both the technical owner...

Company: Amazon
Posted Date: 25 Oct 2025

Senior Staff Digital SOC Engineer - AMS

Responsibilities MaxLinear is seeking a Senior Staff Digital SOC Engineer to join our Analog Mixed Signal (AMS... systems, digital design fundamentals and knowledge of CMOS logic fundamentals. Engineer should be well versed in industry...

Company: MaxLinear
Posted Date: 25 Sep 2025

Design Implementation Engineer, Senior

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.... Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance...

Company: Qualcomm
Posted Date: 08 Nov 2025

CPU Physical Design Engineer, Senior Staff

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... methodology. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently...

Company: Qualcomm
Posted Date: 01 Nov 2025

PD Extraction Engineer, Senior

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.... Job description: Role requirement is for CAD engineer with 3-4 years work experience in the Signoff CAD Team at Qualcomm BDC. The team...

Company: Qualcomm
Posted Date: 08 Oct 2025

AI ML Senior Engineer, Lead

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... or STA Tooling & Infrastructure: Proficient in Python, PyTorch/TensorFlow, Scikit-learn, Pandas, NumPy 6+ years...

Company: Qualcomm
Posted Date: 02 Oct 2025

Physical Design Engineer, Senior Staff

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding...

Company: Qualcomm
Posted Date: 25 Sep 2025

Staff/ Senior Staff DFT Engineer

design, synthesis, STA, and physical design flows. Hands‑on scripting experience (TCL, Python, Perl, Shell...

Company: Marvell
Posted Date: 22 Nov 2025

Senior ASIC Design Engineer

engineering Have a minimum 2 years of RTL design experience Strong experience in Synthesis, STA and constraints development...

Company: Nokia
Posted Date: 22 Nov 2025

Senior Physical Design Engineer

plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work... ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good...

Company: Nvidia
Posted Date: 13 Nov 2025

Lead IP / RTL SOC Design Engineer

your career. SMTS SILICON DESIGN ENGINEER Drive and lead execution with SOC teams for Design. Drive efficiency on execution..., deliverables, risk/ mitigations. Presenting status update to senior executives. Good understanding of sign-off flows like Lint...

Posted Date: 09 Sep 2025

Lead IP / RTL Design integration Engineer

. Presenting status update to senior executives. Good understanding of sign-off flows like Lint, CDC, RDC, Formal Equivalence, Low... implementation/signoff tools, STA and constraints analysis tools. Expertise in SOC architecture, System bus and IO protocol...

Posted Date: 10 Sep 2025

Associate II - VLSI

from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes... work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks...

Company: UST
Posted Date: 29 Oct 2025

DFx Timing

your career. SENIOR SILICON DESIGN ENGINEER : DFX Timing THE ROLE: As a member of the G&E SoC DFT Team, the... constraints and timing closure. Expertise in STA tools Strong understanding of advanced STA concepts and challenges in advanced...

Posted Date: 25 Oct 2025