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Keywords: Implementation Timing / STA Design Engineer, Location: Santa Clara, CA

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Implementation Timing / STA Design Engineer

, STA, and timing closure for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation... for all. Qualcomm’s SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 08 Jun 2025
Salary: $126700 - 190100 per year

Senior ASIC Physical Design and Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...-planning, timing constraints, timing and power convergence, and ECO implementation. Work in a cross-functional environment...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Jun 2025

Senior Staff Physical Design Engineer - Static Timing Analysis

a Senior Staff Physical Design Engineer – Static Timing Analysis (STA) to join our growing team. In this role...: RTL, synthesis, physical implementation, and signoff Debug and resolve complex timing violations and drive design fixes...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 31 May 2025
Salary: $124420 - 186400 per year

Senior ASIC Timing Engineer

design/Timing. Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management..., optimization, and ECO implementation e.g. cell sizing, buffering, vt swap. Hands-on knowledge of industry standard Timing/STA EDA...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 12 Jun 2025

Senior High-Performance ASIC Timing Engineer

+ years’ experience in ASIC Design and Timing Hands-on experience in STA tools, ECO implementation, and timing closure... for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 26 Mar 2025

Senior Staff Engineer, Physical Design

architectures and full-chip physical design a plus. Strong experience in static timing analysis (STA), with a focus on timing... and global timing teams will ensure smooth end-to-end design processes and successful delivery of best-in-class products. As the...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 11 Jun 2025
Salary: $124420 - 186400 per year

Senior ASIC Design Engineer - DFX

We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades... be doing: As a key member of the DFX methodology team, you will be responsible for the architecture, design, implementation...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 May 2025

SoC Design Engineer

timing control design and STA. Perform chip bring-up, validation and debugging. Design, integrate and validate ISP data... level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 30 Apr 2025
Salary: $151091 - 155000 per year

Physical Design Methodology CAD Engineer

. - Developing innovative solutions in physical design and optimization space. - Developing and supporting implementation flows... for multiple projects and design teams. - Developing and maintaining custom CAD tools for implementation and signoff. - Creating...

Company: Apple
Location: Santa Clara, CA
Posted Date: 02 Apr 2025