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Keywords: Senior ASIC Test Timing Engineer, Location: Santa Clara, CA

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Senior ASIC Test Timing Engineer

, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer... inventiveness and intelligence. What you'll be doing: Drive timing analysis and closure of Nvidia’s GPUs, CPUs, DPUs and SoCs...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Oct 2025

Senior ASIC Design Engineer - DFX

We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades... to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Oct 2025

Senior ASIC Engineer

for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches.... Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 02 Nov 2025
Salary: $126700 - 190100 per year

Senior Principal Digital IC Design Engineer

, place and route, and timing signoff. Collaborate with the verification team on pre-silicon verification tasks... such as reviewing test plans, coverage closure, and full-chip simulation debug. Plan, scope, and time tasks with the project manager...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

Senior Staff Application Engineer

of various aspects of ASIC design flow, including design, layout, simulation, and timing analysis, to identify potential issues..., and Test Engineers. Generate professional test reports and conduct comparative performance analyses of test devices...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 21 Sep 2025
Salary: $121400 - 181800 per year

Principal Technical IP Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff... Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering is the center hub...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Nov 2025
Salary: $143200 - 214500 per year

Digital IC design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff... Engineer with Marvell, you’ll be a member of the Custom compute and solutions group. Our design team works on state-of-the-art...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Nov 2025
Salary: $121400 - 181800 per year

AI/ML Design Verification Methodology Lead Engineer

of test benches by adopting emerging techniques and tools. Act as a technical point of contact to the different IP and SoC... Over 5 years of ASIC/SoC verification experience, with at least 2 years in a leadership role. Experience with various...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 09 Oct 2025